The present invention relates to a solid state circuit having a plurality of integrated circuit elements each having at least two output terminals, which solid state circuit is provided with means for determining the operability of each individual element.
Solid state circuits have recently been developed in which a very large number of individual elements are combined into a single component. One example of such an integrated circuit is a semiconductor memory device which contains several thousand individual memories each of which itself consists of a number of active and passive circuit elements which, as is conventional, are fashioned as bipolar elements or by so-called MOS manufacturing processes. Such relatively complicated devices require the use of a large number of complicated manufacturing steps, and experience has shown that, the state of the art being what it is, it is simply not possible to produce absolutely perfect integrated circuits, i.e., it is inevitable that at least some of the individual elements incorporated in the integrated circuit will not function in the desired manner. In fact, experience has shown that as the number of individual elements within an integrated circuit increases, the number of defective elements rises exponentially. It is, therefore, essential that various inspections be performed during, and particularly upon completion of, the manufacturing process, so as to select those integrated circuits which are suitable to carry out their intended function.
There exist testing procedures for integrated circuits having a large number of individual elements in which signals are applied to the circuit, or to individual elements, which signals are then evaluated electronically in order to allow the inspector to determine which of the completed integrated circuits are still usable. It will be appeciated that this is an expensive and cumbersome procedure, particularly in the case of integrated circuits incorporating a large number of individual elements.